CPOL is the 1st bit of SPIx_CR1, controlling the idle state of CLK pin of a specific SPI.
So if you want to remain SCK pin in low state when idle, try:
SPI1->CR1 &= 0xFFFE;
You can also configure the clock polarity in STM32CubeMX: screenshot.
I haven’t try these by myself, but according to the official document, these two method should work. Official STM32L47xxx Reference
42.4.6 Communication formats
Clock phase and polarity controls Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits in the SPIx_CR1 register. The CPOL (clock polarity) bit controls the idle state value of the clock when no data is being transferred. This bit affects both master and slave modes. If CPOL is reset, the SCK pin has a low-level idle state. If CPOL is set, the SCK pin has a high-level idle state.
Bit 1 CPOL: Clock polarity
0. CK to 0 when idle
1: CK to 1 when idle
Note: This bit should not be changed when communication is ongoing.
This bit is not used in SPI TI mode except the case when CRC is applied at TI mode.
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