The size of physical address space for a CPU is an arbitrary choice made by the designers. The width of cache tags and TLB entries have to be wide enough because caches are physically tagged (including L1d in most CPUs, including all Intel), and other internal things that deal with physical addresses. (Like the store buffer, for matching load addresses against outstanding stores. And also for matching stores against in-flight code addresses.)
All Haswell-client CPUs share the same core microarchitecture, so even though a laptop chip doesn’t need that much, some single-socket non-Xeon desktops might. (I think this is true; saving a small amount of space and/or power by changing cache tag widths by 1 or 2 bits might plausible but IDK if Intel does that; I think they really only want to validate a design once.)
Remember that device memory (including PCIe card such as VGA or a Xeon Phi compute card) will normally be mapped into physical address space so the CPU can access it with loads/stores (after pointing virtual pages at those regions of physical address space). PCIe uses fixed width links and sends addresses as part of message “packets”; no extra pins are required for more addresses.
The DDR3 DRAM controllers have a number of address lines on each channel to send row/column addresses; it might be possible to leave one pin unused. It’s very similar to other DDR versions; Wikipedia has diagram of some of the signals in the DDR4 article: https://en.wikipedia.org/wiki/DDR4_SDRAM#Command_encoding
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